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LTC1799
5
1799fc
pin FuncTions
V+ (Pin 1): Voltage Supply (2.7V ≤ V+ ≤ 5.5V). This sup-
ply must be kept free from noise and ripple. It should be
bypassed directly to a ground plane with a 0.1F capacitor.
GND (Pin 2): Ground. Should be tied to a ground plane
for best performance.
SET (Pin 3): Frequency-Setting Resistor Input. The value
of the resistor connected between this pin and V+ deter-
mines the oscillator frequency. The voltage on this pin is
held by the LTC1799 to approximately 1.13V below the
V+ voltage. For best performance, use a precision metal
film resistor with a value between 10k and 200k and limit
the capacitance on this pin to less than 10pF.
DIV (Pin 4): Divider-Setting Input. This three-state input
selects among three divider settings, determining the
value of N in the frequency equation. Pin 4 should be tied
to GND for the ÷1 setting, the highest frequency range.
Floating Pin 4 divides the master oscillator by 10. Pin 4
should be tied to V+ for the ÷100 setting, the lowest fre-
quency range. To detect a floating DIV pin, the LTC1799
attempts to pull the pin toward midsupply. This is realized
with two internal current sources, one tied to V+ and Pin
4 and the other one tied to ground and Pin 4. Therefore,
driving the DIV pin high requires sourcing approximately
5A. Likewise, driving DIV low requires sinking 5A.
When Pin 4 is floated, preferably it should be bypassed
by a 1nF capacitor to ground or it should be surrounded
by a ground shield to prevent excessive coupling from
other PCB traces.
OUT (Pin 5): Oscillator Output. This pin can drive 5kΩ
and/or 10pF loads. Larger loads may cause inaccuracies
due to supply bounce at high frequencies. Transients will
not cause latchup if the current into/out of the OUT pin is
limited to 50mA.
block DiagraM
–
+
+–
1
3
GAIN = 1
V+
VBIAS
IRES
RSET
SET
GND
MASTER OSCILLATOR
PROGRAMMABLE
DIVIDER
(÷1, 10 OR 100)
VRES = 1.13V ±25%
(V+ – VSET)
IRES
(V+ – VSET)
MO = 100MHz kΩ
THREE-STATE
INPUT DETECT
GND
V+
5A
1799 BD
5A
OUT
DIVIDER
SELECT
5
DIV
4
2
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